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? semiconductor components industries, llc, 2010 october, 2010 ? rev. 2 1 publication order number: ncp3121/d ncp3121 dual 3.0 a, step-down dc/dc switching regulator the ncp3121 is a dual buck converter designed for low voltage applications requiring high efficiency. this device is capable of producing an output voltage as low as 0.8 v. the ncp3121 provides dual 3.0 a switching regulators with an adjustable 200 khz ? 750 khz switching frequency. the switching frequency is set by an external resistor. the ncp3121 also incorporates an auto ? tracking and sequencing feature. protection features include cycle ? by ? cycle current limit and undervoltage lockout (uvlo). the ncp3121 comes in a 32 ? pin qfn package. features ? input voltage range from 4.5 v to 13.2 v ? 12 v in to 5.0 v out = 85% efficiency min @ 3.0 a ? 200 ? 750 khz operation ? stable with low esr ceramic output capacitor ? 0.8 1.5% fb reference voltage ? external soft ? start ? out of phase operation of out1 & out2 ? auto ? tracking and sequencing ? enable/disable capability ? hiccup overload protection ? low shutdown power (i q < 100 a) typical applications ? set ? top boxes, portable applications, networking and telecommunications ? dsp/ p/fpga core figure 1. typical application circuit enable disable r_track vin out1 out2 gnd gnd gnd gnd gnd gnd rt r23 c23 d21 r21 r22 c21 gnd d11 gnd gnd c1 c2 gnd gnd r11 r12 c11 l11 l21 pg1 pg2 en1 seq1 en2 seq2 track1,2 sw1 vin sw2 avin fb1 gnd comp1 ss1 ss2 comp2 agnd fb2 rt gnd r13 c13 c22 r24 r14 en2 en1 pg1 pg2 agnd c12 enable disable ncp3121 rvin gnd c3 marking diagram http://onsemi.com 32 1 ncp3121 awlyyww 1 ncp3121 = specific device code a = assembly location wl = wafer lot yy = year ww = work week = pb ? free package qfn32 case 488am (note: microdot may be in either location) see detailed ordering and shipping information in the package dimensions section on page 40 of this data sheet. ordering information
ncp3121 http://onsemi.com 2 figure 2. block diagram reference 0. 8v oscillator star tu p uvl o th er mal sh u td own fb1 0. 5v con tr ol logic 2 con tr ol logic 1 power sequencing 1 power sequencing 2 soft start & tracking control (mux1) soft start & tracking control (mux2) delay pwm 0 .9 . ref 0 .1. ref shdn 2 s r shdn 1 shdn 2 avin ref (0 .8v ) ref (0.8 v) 180 o 0 o hs 2 hs 1 0 .5v fb2 1v ss 2 1 v ss 1 10u 10u 10 u 10 u eota 2 pwm s r eota 1 0 .9 . ref 0 .1. ref shdn 1 delay pg 1 overload protection hs protection 1 overload protection hs protection 2 error amplifier error amplifier signal voltage falling comp falling comp pg 2 shdn2 shdn1 shdn2 shdn 1 pg 1 vin sw 1 gnd 1 avin agnd gnd 2 vin sw 2 pg 2 comp 1 fb 1 ss 1 track 1 rt en 1 en 2 seq 1 seq 2 ref (0.8 v) ss 2 track 2 comp 2 fb 2
ncp3121 http://onsemi.com 3 pin description pin symbol description 1, 31, 32 sw1 switch node of channel 1. connect an inductor between sw1 and the regulator output. 2 ? 7 v in input power supply voltage pins. these pins should be connected together to the input signal supply voltage pin. 8 ? 10 sw2 switch node of channel 2. connect an inductor between sw2 and the regulator output. 11 gnd2 power ground for channel 2 12 ss2 soft ? start control input for channel 2. an internal current source charges an external capacitor connected to this pin to set the soft ? start time. 13 comp2 compensation pin of channel 2. this is the output of the error amplifier and inverting input of the pwm comparator. 14 agnd analog ground; connect to gnd1 and gnd2. 15 fb2 feedback pin. used to set the output voltage of channel 2 with a resistive divider from the output. 16 rt resistor select for the oscillator frequency. connect a resistor from the rt pin to agnd to set the fre- quency of the master oscillator. leave this pin floating, for 200 khz operation. 17 track 2 tracking input for channel 2. this pin allows the user to control the rise time of the second output. this pin must be tied high in the normal operation (except in the tracking mode). 18 track 1 tracking input for channel 1. this pin allows the user to control the rise time of the first output. this pin must be tied high in the normal operation (except in the tracking mode). 19 seq2 sequence pin for channel 2. i/o used in power sequencing. connect seq to en for normal operation of a standalone device. 20 en2 enable input for channel 2. 21 seq1 sequence pin for channel 1. i/o used in power sequencing. connect seq to en for normal operation of a standalone device. 22 en1 enable input for channel 1. 23 pg2 power good, open ? drain output of channel 2. output logic is pulled to ground when the output is less than 90% of the desired output voltage. tied to an external pull ? up resistor. leave this pin floating, if not used. 24 pg1 power good, open ? drain output of channel 1. output logic is pulled to ground when the output is less than 90% of the desired output voltage. tied to an external pull ? up resistor. leave this pin floating, if not used. 25 av in input signal supply voltage pin. 26 fb1 feedback pin. used to set the output voltage of channel 1 with a resistive divider from the output. 27 agnd analog ground. connect to gnd1 and gnd2. 28 comp1 compensation pin of channel 1. this is the output of the error amplifier and inverting input of the pwm comparator. 29 ss1 soft ? start/stop control input for channel 1. an internal current source charges an external capacitor con- nected to this pin to set the soft ? start time. 30 gnd1 power ground for channel 1. exposed pad (gnd) the exposed pad at the bottom of the package is the electrical ground connection of the ncp3121. this node must be tied to ground.
ncp3121 http://onsemi.com 4 maximum ratings characteristics symbol min max unit power supply voltage input v vin ? 0.3 15 v signal supply voltage input v avin ? 0.3 15 v sw pin voltage v sw ? 0.7 ? 5v for < 50 ns v vin v en pin voltage input v en ? 0.3 8.0 v seq pin voltage output v seq ? 0.3 8.0 pg pin voltage v pg ? 0.3 5.5 v all other pins ? ? 0.3 5.5 v thermal resistance, junction ? to ? ambient (note 1) r ja 50 c/w storage temperature range t stg ? 55 to +150 c junction operating temperature (note 2) t j ? 40 to +150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. r ja on a 100 x 100 mm pcb with two solid 1 oz ground planes. 2. the maximum package power dissipation limit must not be exceeded p d t j(max) t a r ja
ncp3121 http://onsemi.com 5 electrical characteristics ( ? 40 c < t j < 125 c, t j = 25 c for typical values, v avin =12 v, v vin =12 v, unless otherwise noted. r t = open k ) characteristic conditions min typ max unit recommended operating conditions input voltage range 4.5 13.2 v supply current quiescent supply current v en = h, v fb = 1.0 v no switching, pg open 5.0 7.0 ma shutdown supply current v en = 0 v, pg open 100 a undervoltage lockout uvlo threshold v in rising edge v in falling edge 3.9 4.3 4.1 4.5 v uvlo hysteresis 0.15 0.20 0.25 v switching regulator minimum duty cycle comp = 0.6 v 0 % maximum duty cycle comp = 2.6 v 90 % high side mosfet r ds(on) i sw = 0.5 a, t j = 25 c 250 m high side leakage current v en = 0v, v sw = 0v 10 a high side switch current limit set point (note 3) 3.5 4.15 4.8 a current loop transient response (note 4) 100 nsec fb v fb feedback voltage t j = 25 c t j = ? 40 to 125 c, 4.5 v < v in < 13.2v 0.788 0.784 0.8 ? 0.812 0.816 v osc oscillator frequency t j = 25 c, t j = ? 40 to 125 c t j = 25 c, t j = ? 40 to 125 c (rt = 52.3 k ) 180 170 635 200 200 750 220 230 865 khz khz khz standard oscillator frequency range t j = 25 c 200 750 khz transconductance error amplifier (gm) transconductance (note 4) 0.9 1.0 1.1 ms dc gain (note 4) 50 55 60 db unity gain bandwidth (note 4) 4.0 mhz output sink current v fb = 1.0 v, vcomp = 1.5 v 80 100 a output source current v fb = 0.6 v, vcomp = 1.5 v 80 100 a input bias current v fb = 0.8 v 100 500 na comp pin operating voltage range (note 4) 0.6 2.6 v soft ? start soft ? start period v fb < 0.8 v, c s = 0.1 f 10 ms soft ? start voltage range 0 v fb v soft ? start current source charging, v ss = 1 v discharging, v ss = 1 v 6.0 6.0 8.0 8.0 12 12 a a
ncp3121 http://onsemi.com 6 electrical characteristics ( ? 40 c < t j < 125 c, t j = 25 c for typical values, v avin =12 v, v vin =12 v, unless otherwise noted. r t = open k ) characteristic unit max typ min conditions track tracking voltage range 0 v fb v tracking voltage offset v track = 0.6 v 15 mv track bias current v track = 0.6 v 100 500 na power good pg threshold feedback voltage rising, en tied to seq, v pg = 3.3 v 90% v fb v pg shutdown mode feedback voltage falling, en tied to seq, v en,seq = 0v, v pg = 3.3v 10% v fb 15% v fb 20% v fb v pg delay rising edge of v out falling edge of v out 50 10 s s pg low level voltage i (pg) = 1 ma 0.3 v pg hysteresis 45 mv pg leakage current v pg = 5.5 v 1.0 a enable/power sequencing enable internal pullup current 4.0 a sequence internal pulldown current 16 a enable threshold high en tied to seq 2.0 v sequence threshold low en tied to seq 0.8 v thermal shutdown overtemperature trip point (note 4) 160 c hysteresis 15 c 3. dc value. 4. guaranteed by design.
ncp3121 http://onsemi.com 7 typical operating characteristics figure 3. feedback voltage vs. temperature figure 4. high switching frequency vs. temperature temperature ( c) temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 0.783 0.788 0.793 0.798 0.803 0.808 0.813 125 100 75 50 25 0 ? 25 ? 50 730 750 770 790 810 830 850 figure 5. low switching frequency vs. temperature figure 6. quiescent supply current vs. temperature temperature ( c) temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 186 191 196 201 206 211 216 125 100 75 50 25 0 ? 25 ? 50 0 1 2 3 4 5 6 voltage (v) frequency (khz) frequency (khz) current (ma) rt = 47 k rt = open 1 channel disabled
ncp3121 http://onsemi.com 8 typical operating characteristics figure 7. shutdown supply current vs. temperature figure 8. r ds(on) vs. temperature temperature ( c) temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 0 10 20 50 70 80 100 125 100 75 50 25 0 ? 25 ? 50 0.15 0.20 0.25 0.35 0.40 figure 9. uvlo ? rising threshold vs. temperature figure 10. current limit vs. temperature temperature ( c) temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 4.20 4.25 4.30 4.35 4.40 4.45 4.50 125 100 75 50 25 0 ? 25 ? 50 3.8 3.9 4.0 4.1 4.2 4.3 4.4 figure 11. uvlo ? falling threshold vs. temperature figure 12. soft ? start charge current vs. temperature temperature ( c) temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 3.90 3.95 4.00 4.05 4.10 4.15 4.20 125 100 75 50 25 0 ? 25 ? 50 6.9 7.4 7.9 8.4 8.9 9.4 9.9 current ( a) r ds(on) ( ) voltage (v) current (a) voltage (v) current ( a) 0.30 30 40 60 90
ncp3121 http://onsemi.com 9 typical operating characteristics figure 13. soft ? start discharge current vs. temperature figure 14. power good hysteresis vs. temperature temperature ( c) temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 6.9 7.4 8.4 8.9 9.9 125 100 75 50 25 0 ? 25 ? 50 20 30 35 50 60 70 figure 15. tracking voltage offset vs. temperature figure 16. power good rising delay vs. temperature temperature ( c) temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 ? 15 ? 10 ? 5 0 5 10 15 125 100 75 50 25 0 ? 25 ? 50 35 40 45 50 55 60 65 figure 17. power good feedback threshold vs. temperature figure 18. power good falling delay vs. temperature temperature ( c) temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 0.71 0.73 0.75 0.77 0.79 0.81 0.83 125 100 75 50 25 0 ? 25 ? 50 5 7 9 11 13 15 17 current ( a) voltage (mv) voltage (mv) delay ( s) voltage (v) delay ( s) 40 7.9 9.4 25 45 55 65 v track = 0.6 v
ncp3121 http://onsemi.com 10 typical operating characteristics figure 19. power good saturation voltage vs. temperature figure 20. en internal pull ? up current vs. temperature temperature ( c) temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 0 0.05 0.10 0.25 0.30 0.40 0.45 125 100 75 50 25 0 ? 25 ? 50 2.0 2.5 3.0 3.5 4.0 5.0 5.5 6.0 figure 21. power good current vs. drain ? to ? source voltage figure 22. seq internal pull ? down current vs. temperature vds (v) temperature ( c) 4.5 4.0 3.0 2.0 1.5 1.0 0.5 0 0 2 4 6 8 10 12 125 100 75 50 25 0 ? 25 ? 50 10 11 12 13 16 17 19 20 figure 23. ncp3121 line regulation figure 24. ncp3121 load regulation vin (v) iout (a) 15 13 11 9 7 5 3.20 3.22 3.24 3.28 3.32 3.34 3.38 3.40 2.0 1.5 1.0 0.5 0 3.3 3.303 3.306 3.309 3.312 3.318 voltage (v) current ( a) ids (ma) current ( a) vout (v) vout (v) 0.15 0.20 0.35 4.5 2.5 3.5 5.0 14 15 18 3.26 3.30 3.36 v in = 12 v v in = 5 v i out = 50 ma 3.315 3.0 2.5
ncp3121 http://onsemi.com 11 typical operating characteristics figure 25. ncp3121 efficiency, v in = 12 v, v out = 3.3 v, 25 c i out (a) 2.0 1.5 1.0 0.5 0 55 60 65 70 75 80 85 90 figure 26. ncp3121 efficiency, v in = 12 v, v out = 5 v, 25 c figure 27. r ds(on) vs. input voltage i out (a) vin = avin (v) 2.0 1.5 1.0 0.5 0 55 60 65 75 80 90 95 14 12 10 9 8 7 5 4 0.20 0.25 0.30 0.35 0.40 0.45 0.50 efficiency (%) efficiency (%) r ds(on) ( ) 12 v 200 khz 500 khz 750 khz 70 85 61113 12 v 200 khz 500 khz 750 khz 3.0 2.5 3.0 2.5 figure 28. maximum currents vs. operating frequency due to toff min limitations 3.3 vout frequency (khz) 550 500 450 400 350 300 250 200 0 0.5 1.0 2.5 output current (a) 1.5 2.0 4.5 v in 750 700 650 600 figure 29. maximum currents vs. operating frequency due to toff min limitations 1.8 vout figure 30. minimum input voltage vs. operating frequency, 3a, 3.3 vout frequency (khz) 550 500 450 400 350 300 250 200 5.5 5.6 5.7 6.0 minimum input voltage (v) 5.8 5.9 75 0 700 650 600 3.5 3.0 5.0 v in 5.5 v in frequency (khz) 550 500 450 400 350 300 250 200 0 0.5 1.0 2.5 output current (a) 1.5 2.0 4.5 v in 750 700 650 600 3.5 3.0 5.0 v in
ncp3121 http://onsemi.com 12 typical operating characteristics figure 31. minimum input voltage vs. operating frequency, 3a, 1.8 vout figure 32. minimum input current 3.3 vout output current (a) 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 input current (a) 2.5 12 v in two outputs 3.0 2.5 12 v in one output frequency (khz) 550 500 450 400 350 300 250 200 4.8 4.9 5.0 5.3 minimum input voltage (v) 5.1 5.2 750 700 650 600 4.85 4.95 5.25 5.05 5.15 figure 33. minimum input voltage 5 vout, 350 khz figure 34. minimum input voltage 3.3 vout, 350 khz vin (v) vin (v) 6.25 6.0 5.5 5.0 4.75 4.5 0 1 2 3 4 5 6 5.0 4.75 4.5 0 0.5 1 1.5 3 vout (v) vout (v) 5.25 5.75 6.5 2 2.5 0.1 a 0.5 a 1.5 a 2.0 a 2.5 a 1.5 a 2.0 a 0.5 a 1.0 a 0.1 a 6.75 1.0 a 3.0 a 5.25 5.5 2.5 a 3.0 a 3.5
ncp3121 http://onsemi.com 13 detailed description introduction the ncp3121 is a dual channel non ? synchronous pwm voltage mode buck regulator. each channel is identical and has a 3.0 a internal p ? fet, compensation, feedback, programmable soft ? start, enable and power good pins. these circuits also share the same input voltage, reference voltage, thermal shutdown, undervoltage detect and master oscillator. a simple auto ? tracking and sequencing capability can be implemented using the seq/track/ss pins. the fixed ? frequency programmable architecture, driven from a common oscillator, ensures a 180 phase differential between channels. this 180 phase shift between the two channels reduces the common input capacitor requirement and improves the noise immunity. the ncp3121 switching frequency is set by an external resistor and is adjustable between 200 ? 750 khz. this allows application optimization between efficiency and total solution size. the output voltage is fed back through an external resistor voltage divider to the fb input pin and compared with the reference voltage, then the voltage difference is amplified through the internal transconductance error amplifier. the output current of the transconductance error amplifier (ota) is presented at the comp node where an rc network compensates the regulation control system loop. the ncp3121 features a programmable soft ? start function, which is implemented through the error amplifier and the external compensation capacitor. this feature prevents stress to the power components and limits output voltage overshoot during start ? up. undervoltage lockout (uvlo) undervoltage lockout (uvlo) is provided to ensure that unexpected behavior does not occur when v in is too low to support the internal rails and power the converter. in case the input voltage is higher than the uvlo threshold (4.3 v standard value, rising voltage), the step down converter operation can be started. this circuit has a 0.2 v hysteresis (typical). if the falling trip is activated, switching ceases and eventually the circuit turns off. when the input circuit is in this state, the currrent consumption is equal 5 ma (typical). fixed frequency operation the ncp3121 uses a constant frequency architecture for generating a pwm signal. during normal operation, the oscillator generates an accurate pulse at the beginning of each switching cycle to turn on the main switch. the main switch will be turned off when the ramp signal intersects with the output of the error amplifier (comp pin voltage). therefore, the switch duty cycle can be modified to regulate the output voltage to the desired value as line and load conditions change. the major advantage of fixed frequency operation is that the component selections, especially the magnetic component design, become very easy. the oscillator frequency of the ncp3121 is programmable from 200 khz to 750 khz using an external resistor connected from the rt pin to ground. the oscillator works on the double frequency internally. therefore, both channels have a 180 phase shift of the sw pins. out ? of ? phase operation in out ? of ? phase operation, the turn ? on of the second channel is delayed by half the switching cycle. this delay is supervised by the oscillator, which supplies a clock signal to the second channel which is 180 out of phase with the clock signal of the first channel. the advantages of out ? of ? phase synchronization are many. since the input current pulses are interleaved with one another, the overlap time is reduced. the effect of this overlap reduction is to attenuate the input filter requirement, allowing the use of smaller components. additionally, since peak current occurs during a shorter time period, emitted emi is also reduced, thereby reducing shielding requirements. enable input pull the en enable input high to enable operation. the en high signal must occur after vin has exceeded 2.7 v to allow internal power-on reset (por) logic to initialize the ic. logic low on seq forces the ncp3121 into shutdown mode. connect seq to en for normal operation of a standalone device. in shutdown mode, the ncp3121 is turned off and the supply current is reduced to less than 100 a. when the enable function is not required, float the en connection. the ncp3121 will turn itself on once vin crosses the input uvlo threshold. do not pull en to vin or a separate supply voltage . for standalone operation, en should still be connected to seq. note: for proper operation of the ncp3121 circuit, no voltage may be pulled high on the output pins. the output capacitors should be discharged. if this condition is not observed when ncp3121 is enabled, the regulator does not start switching. this helps to prevent improper operation of the ncp3121 circuit due to the implemented tracking and sequencing features. soft ? start/stop control this capacitor limits the maximum demand on the external power supply by controlling the inrush current peaks to charge the output capacitor and dc load and to attain smoothly increasing output voltage at start ? up. a soft start circuit forces the error amplifier output to follow a prescribed voltage ramp when turning on and off. the output capacitor is discharged when v in goes under the uvlo as thermal shutdown or overload detection occurs. the circuit input is presented as a voltage ramp generated by internal current sources tied to an external ss capacitor. the external capacitor on the soft ? start node is char ged/dischar ged by the 8.75 a current from the constant current source, and the voltage on the ss node controls the ota amplifier output
ncp3121 http://onsemi.com 14 voltage until the ss capacitor is charged/discharged to a voltage higher than 0.8 v. power good the power good is an open drain and active high output that indicates when the output voltage has reached 90% (min) of the nominal output voltage. this output can be pulled up to the appropriate level with an external resistor. the power good comparator senses the voltage at the fb pin, which is a function of v out . the power good output transistor behavior is shown in the ?typical operating characteristics? section. the pg pin is held low during a soft ? start. once a soft ? start is completed, the pg goes high if there are no faults and no delays associated with it. current limit the ncp3121 protects a power system if overcurrent occurs. the ncp3121 contains pulse ? by ? pulse current limiting to protect the power switch and external components. the current through each channel is continuously monitored. the current limit is set to allow peak switch current in excess of 3.5 a (minimum). current limiting is implemented by monitoring the high ? side p ? channel switch current during conduction with a current limit comparator. when the peak of the switching current reaches the current limit, the power switch turns off. hiccup overload protection (olm ? over load mode) hiccup mode is a method of protecting the power supply from damage during overload conditions. within normal operation, the external soft ? start capacitor is pulled up by a current source that delivers 8.75 a to the ss pin capacitor. the soft ? start capacitor continues to charge until it reaches the saturation voltage of the current source, typically v ss = 4 v. when the overload condition is detected, the soft ? start capacitor is discharged to 0.1 v and is again charged to 1 v. this is periodically repeated until the overload condition is detected. the transconductance error amplifier output is tied to ground when the soft ? start capacitor is discharged. figure 35. hiccup overload protection thermal shutdown the ncp3121 has a thermal shutdown feature to protect the device from overheating when the die temperature exceeds 160 c (typically). if the chip temperature exceeds the overtemperature shutdown trip point, the fault signal is activated. this will disable the step down converter operation, and the chip temperature will start to decrease. when the chip temperature drops 15 c below the overtemperature shutdown trip point, the fault signal is deactivated and the step down converter operation starts again with soft ? start. the thermal event sends the device immediately into the off state. the currrent consumption is equal 5 ma (typical) if the thermal condition is reached.
ncp3121 http://onsemi.com 15 application & design information inductor the output inductor may be the most critical component in the converter because it will directly affect the choice of other components and dictate both the steady state and transient performance of the converter. when choosing inductors, one might have to consider maximum load current, core and copper losses, component height, output ripple, emi, saturation and cos t. lower inductor values are chosen to reduce the physical size of the inductor. a higher value cuts down the ripple current and core losses and allows more output current. in general, the output inductance value should be as low and the output inductor physically as small as possible to provide the best transient response and minimum cost. if a large inductance value is used, the converter will not respond quickly to rapid changes in the load current. on the other hand, an inductance value that is too low will result in very large ripple currents in the power components, resulting in increased dissipation and lower converter efficiency. a good standard for determining the inductance to use is to select the inductor peak ? to ? peak ripple current to be approximately 25% of the maximum switch current. also, make sure that the inductor peak current is below the maximum switch current limit and the selected inductor type saturation current specification is higher than the peak current through the switch. the maximum current in the inductor while operating in the continuous current mode is defined as the load current plus one half of the i l currrent: i lp i load 1 2 i l the inductance value can be calculated by: l v out v in v out v in i l f osc therefore, the inductor peak current, i lp , can be calculated by: i lp i load v out v in v out 2 v in l f osc where; i load is the output load current v out is the output voltage v in is the input voltage i l is the peak ? to ? peak inductor ripple current f osc is the switching frequency of the oscillator the choice of the appropriate inductor type depends not only on the calculated inductance value, saturation current rating and parasitic serial resistance, but also on the required physical dimensions, emi requirements (shielded or open inductor) and the price. examples of suitable inductors from various manufacturers are shown in the table below. table 1. calculated inductor values calculated coils, i ripple peak ? peak 20% f [khz] 200 350 500 750 i out [a] 12 v in to 7.5 v out 2 a 36 h 20 h 14 h 10 h 3 a 24 h 14 h 10 h 6.5 h 12 v in to 5 v out 2 a 36 h 20 h 15 h 10 h 3 a 24 h 14 h 10 h 6.5 h 12 v in to 3.3 v out 2 a 30 h 17 h 12 h 8 h 3 a 20 h 12 h 8 h 5.4 h 5 v in to 3.3 v out 2 a 14 h 8 h 5.6 h 3.7 h 5 v in to 2.5 v out 2 a 16 h 9 h 6.3 h 4 h 5 v in to 1.8 v out 2 a 15 h 8.2 h 5.8 h 3.8 h 3 a 10 h 5.5 h 3.8 h 2.6 h
ncp3121 http://onsemi.com 16 table 2. inductor examples l [ h] part number shielded/ non ? shielded i rms [a] dcr max [m } manufacturer web 33 do5010h ? 333 n 3.0 66 coilcraft www.coilcraft.com pf0382.333nl n 3.1 65 pulse www.pulseeng.com mss1278 ? 333 s 3.1 80 coilcraft www.coilcraft.com 74458133 n 3.0 66 we www.we ? online.com pf0552.333nl s 3.7 54.1 pulse www.pulseeng.com 22 ds5022p ? 223 s 3.1 59 coilcraft www.coilcraft.com p0648.223 n 3.3 61 pulse www.pulseeng.com 74458122 n 3.5 47 we www.we ? online.com mss1246t ? 223 s 3.14 70 coilcraft www.coilcraft.com pf0382.223nl n 3.5 47 pulse www.pulseeng.com 15 do3316p ? 153 n 3.1 46 coilcraft www.coilcraft.com p0751.153nl n 3.0 46 pulse www.pulseeng.com mss1260t ? 153 s 3.5 40 coilcraft www.coilcraft.com 74459115 s 3.5 48 we www.we ? online.com 74458115 n 4.0 36 we www.we ? online.com 10 do3340p ? 103 n 3.5 40 coilcraft www.coilcraft.com ds5022p ? 103 s 3.9 42 ?coilcraft www.coilcraft.com 7445610 n 3.3 45 we www.we ? online.com 74459010 s 3.9 40 we www.we ? online.com do3316p ? 103 n 3.5 34 coilcraft www.coilcraft.com p0751.103nl n 3.8 38 pulse www.pulseeng.com 9 p1169.123nl s 3.5 37 pulse www.pulseeng.com 8.2 ds3316t ? 822 n 4.15 32 coilcraft www.coilcraft.com mss1246 ? 822 s 4.67 35 coilcraft www.coilcraft.com 6.8 74456068 n 3.8 34 we www.we ? online.com 5.6 do33165 ? 562 n 4.65 21 coilcraft www.coilcraft.com 74456056 n 4.0 32 we www.we ? online.com do5022p ? 562 s 4.1 3 coilcraft www.coilcraft.com 5.0 mss7341 ? 502 s 4.7 24 coilcraft www.coilcraft.com 3.3 do3316p ? 332 s 4.7 26 coilcraft www.coilcraft.com ds5022p ? 332 s 3.3 39 coilcraft www.coilcraft.com output rectifier diode when the high ? side switch is on, energy is stored in the magnetic field in the inductor. during off time, the internal mosfet switch is off. since the current in the inductor has to discharge, the current flows through the rectifying diode to the output. a schottky diode is recommended due to low diode forward voltage and very short recovery times, which positively impacts the step down voltage converter?s overall efficiency. another choice could be fast recovery or ultra ? fast recovery diodes. it should be noted that some types of these diodes with an abrupt turn ? off characteristic may cause instability or emi troubles. the peak reverse voltage is equal to the maximum input voltage. the peak conducting current is clamped by the current limit of the ncp3121. use of schottky barrier diodes reduces diode reverse recovery input current spikes. for switching regulators operating at low duty cycles, it is beneficial to use rectifying diodes with somewhat higher rms current ratings (thus lower forward voltages). this is because the diode conduction interval is much longer than that of the transistor. converter efficiency will be improved if the voltage drop across the diode is lower. the average current can be calculated from: i d(avg) i load v in v out v in
ncp3121 http://onsemi.com 17 table 3. schottky diode example part number description v rrm min [v] v f max [v] i o(rec) max [a] package web mbra340t3g 3 a, 40 v schottky rectifier 40 0.45 3 sma www.onsemi.com mbrs340t3g 3 a, 40 v schottky rectifier 40 0.5 3 smc www.onsemi.com mbrs330t3g 3 a, 30 v schottky rectifier 30 0.5 3 smc www.onsemi.com the worst case of the diode average current occurs during maximum load current and maximum input voltage. the rectifying diodes should be placed close to the sw pin to avoid the possibility of ringing due to trace inductance. input capacitor the input current to the step down converter is discontinuous. the input capacitor has to maintain the dc input voltage and to sustain the ripple current produced by internal mosfet switching. for stable operation of the switch mode converter, a low esr capacitor is needed to prevent lar ge voltage transients from appearing at the input. therefore, ceramic capacitors are preferred, but the circuit works in a stable manner also with electrolytic capacitors. it must be located near the regulator and use short leads. also, paralleling ceramic capacitors will increase the regulator stability. the rms value of the input capacitor current ripple is: i rms i load d ( 1 d ) the duty cycle is: d v out v d v in v d v dsat where: v d is the voltage drop across the rectifying diode and v dsat is the switch saturation voltage on the power mosfet. the equation reaches its maximum value with duty cycle = 0.5, where: i rms i load 2 losses in the input capacitor can be calculated using the following equation: p cin i rms 2 esr cin where: esr cin is the effective series resistance of the input capacitance. the input capacitor voltage ripple depends on the c in capacitor value. therefore, the input capacitor can be estimated by: c in i load f sw v in v out v in 1 v out v in output capacitor the output capacitor filters output inductor ripple current and provides low impedance for load current changes. the principle consideration for the output capacitor is the ripple current induced by the switches through the inductor. it supplies the current to the load in dcm or during load transient and filters the output voltage ripple. for low output ripple voltage and good stability, low esr output capacitors are recommended. the inductor ripple current acting against the esr of the output capacitor is the major contributor to the output ripple voltage. an output capacitor has two main functions: it filters the output and provides regulator loop stability. the esr of the output capacitor and the peak ? to ? peak value of the inductor ripple current are the main factors contributing to the output ripple voltage value. the output voltage ripple is given by the following equation: v out v out f sw l 1 v out v in esr 1 8 f sw c out where: esr is the equivalent series resistance of the output capacitor. the output capacitor value can by expressed by: c out i l 8 f sw v out i l esr these components must be selected and placed carefully to yield optimal results. key specifications for output capacitors are their esr (equivalent series resistance) and esl (equivalent series inductance) values. for best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required. for most applications, a 22 f ceramic capacitor should be sufficient. x5r or x7r dielectrics ceramic capacitors are recommended. soft ? start capacitor selection the soft ? start time is programmed by an external capacitor connected from the ss pin to agnd, which can be calculated by: c ss t ss 8.75 a 0.8 v where: ? t ss is the soft ? start/stop interval. note: see the ?sequencing and tracking? section on how to use this capacitor.
ncp3121 http://onsemi.com 18 output voltage programming the controller will maintain 0.8 v at the feedback pin. thus, if a resistor divider circuit is placed across the feedback pin to v out , the controller will regulate the output voltage in proportion to the resistor divider network in order to maintain 0.8 v at the fb pin. table 4. output voltage setting v out [v] 8 7.5 6 5 4 3.3 2.5 1.8 1.2 r 1 [k ] 180 360 130 68 300 47 51 20 10 r 2 [k ] 20 43 20 13 75 15 24 16 20 figure 36. feedback divider v out v fb r1 r2 the relationship between the resistor divider network and the output voltage is shown in the following equation: r 2 r 1 v ref v out v ref where: v ref is the circuit?s internal voltage reference, which equals 0.8 v. resistor r1 is selected based on a design trade ? off between efficiency and output voltage accuracy. for high values of r1, there is less current consumption in the feedback network. however, the trade ? off is output voltage accuracy due to the bias current in the error amplifier. once r1 has been determined, r2 can be calculated. selecting the switching frequency selecting the switching frequency is a trade ? off between component size and power losses. operation at higher switching frequencies allows the use of smaller inductor and capacitor values. nevertheless, it is common to select lower frequency operation because a higher frequency results in lower efficiency due to mosfet gate charge losses. additionally, the use of smaller inductors at higher frequencies results in higher ripple current, higher output voltage ripple, and lower efficiency at light load currents. the value of the oscillator resistor is designed to be linearly related to the switching period. there are two ways to determine the rt resistor value: by using the standard curve shown in figure 37 or by using table 5. the frequency on the rt pin will set the master oscillator. the actual operating frequency on each channel will be one ? half the master oscillator. 0 100 200 300 400 500 600 200 250 300 350 400 450 500 550 600 650 700 75 0 freq [khz] rt [kohm] figure 37. switching frequency selection table 5. switching frequency selection freq. [khz] 200 250 300 350 400 450 500 550 600 650 700 750 rt [k ] open 649 316 205 154 121 100 84.5 73.2 64.9 57.6 52.3 sequencing of output voltages some microprocessors and dsp chips need two power supplies with different voltage levels. these systems often require voltage sequencing between the core power supply and the i/o power supply. without proper sequencing, latch ? up failure or excessive current draw may occur that could result in damage to the processor?s i/o ports or the i/o ports of a supporting system device such as memory, an fpga or a data converter. to ensure that the i/o loads are not driven until the core voltage is properly biased, tracking of the core supply and the i/o supply voltage is necessary. designing a system without proper power supply sequencing for signal processing devices like dsps, fpgas, and plds may create risks as to reliability or proper functionality. the risk comes when there are active and inactive power supply rails on the device for a long time. during this time, the esd structures, internal circuits and components are stressed from interference between different voltages (from the two separate power supply rails). when these conditions persist on multi ? supply devices for long time periods (this is a cumulative phenomenon), the life of the products (dsp, fpga, and
ncp3121 http://onsemi.com 19 pld devices) is drastically reduced. the failure is often a result of high currents flowing to the pins or the high voltage difference between pins. in that case, the signal processors require multiple power supplies generating different voltage levels for core and i/o peripherals over time. ncp3121 offers ratiometric sequencing, sequential sequencing and tracking sections to manage the output voltages behavior during start ? up and power ? down. basically, the dsp, fpga, and pld manufacturers do not specify the method of power sequencing, but they do specify restrictions on the time or voltage differences during power ? up and power ? down. the power ? up sequence for microprocessors should be finished approximately within a few seconds to prevent the risks mentioned above. for more information, see the microprocessor manufacturers? datasheets. ratiometric sequencing in the ratiometric sequencing mode, multiple outputs start ramping at the same time and also reach the regulation level at the same time. when common en is pulled down, the output voltages are going down at the same time. see figure 38. this functionality is created by using the same capacitor values as the soft ? start capacitors for all outputs and by connecting all en + seq pins together. to ensure this behavior, the soft start capacitors should have values greater than the time constant of the output inductor and output capacitor. for proper operation in this mode, using a common soft ? start capacitor for both channels is not recommended. note: if enable control is not required, float the en/seq connections rather than pulling them to vin or a separate supply voltage. the ncp3121 will enable itself once vin crosses the input uvlo threshold. vout1 vout2 figure 38. ratiometric sequencing configuration enable disable r_track avin c3 c13 r13 vin out1 out2 gnd gnd gnd gnd gnd gnd gnd c22 r_t r23 c23 d21 r21 r22 c21 gnd d11 gnd gnd c1 c2 gnd gnd r11 r12 c11 l11 l21 pg1 pg2 en1 seq1 en2 seq2 track1 track2 sw1 vin vin vin vin vin vin sw2 avin fb1 agnd comp1 ss1 gnd1 sw1 sw1 sw2 sw2 gnd2 ss2 comp2 agnd fb2 rt c12 en1 ncp3121
ncp3121 http://onsemi.com 20 figure 39. typical behavior of ratiometric sequencing mode en1/seq1 & en2/seq2 ss1 & ss2 vout1 & vout2 pg1 & pg2 hyst + delay 0.8v 0.8v 4v 90% v fb1 (min) 90% v fb2 (min) figure 40. ratiometric mode ? power ? up figure 41. ratiometric mode ? power ? down figure 42. ratiometric mode ? start of olm figure 43. ratiometric mode ? end of olm
ncp3121 http://onsemi.com 21 sequential sequencing (first ? up/last ? down sequence configuration) in sequential sequencing mode, the second output voltage starts ramping when the first output voltage is already settled and its power good signal is set. figure 44 shows the ncp3121?s configuration and standard waveforms. the rising slope of both voltages can be selected independently by the soft ? start capacitors? values (c12, c22). when the enable pin is deactivated, the second output voltage decreases first, followed by the first output voltage. the control logic is based on the internal power good signal; no delay is added. the signal has the same threshold values as the power good signal shown in the electrical table. the sequential sequencing mode is also called first ? up/ last ? down and is ideal for dsps with separate power supplies for the core and the i/o ports. note: if enable control is not required, float the en(first)/seq(last) connection rather than pulling it to vin or a separate supply voltage. for figure 44 this is en1/seq1. for figure 45, this is en1/seq4. the ncp3121 will enable itself once vin crosses the input uvlo threshold. c12 c22 vout1 vout2 c22 c12 figure 44. sequential configuration enable disable r_track avin c3 c13 r13 vin out1 out2 gnd gnd gnd gnd gnd gnd gnd r_t r23 c23 d21 r21 r22 c21 gnd d11 gnd gnd c1 c2 gnd gnd r11 r12 c11 l11 l21 pg1 pg2 en1 seq1 en2 seq2 track1 track2 sw1 vin vin vin vin vin vin sw2 avin fb1 agnd comp1 ss1 gnd1 sw1 sw1 sw2 sw2 gnd2 ss2 comp2 agnd fb2 rt c12 c22 en1 ncp3121
ncp3121 http://onsemi.com 22 daisy chain operation the last ? up/first ? down power output has its seq pin tied to the en of the first ? up/last ? down power output. each output in the chain has its power ? up delay set by the soft ? start ramp ? up of the supply. this feeds its en and its power ? down delay set by the soft ? start ramp ? down of the supply that feeds its seq pin. enable disable seq en ncp3121 track ss seq en ncp3121 track ss seq en ncp3121 track ss c1 c2 c3 seq en ncp3121 track ss c4 figure 45. simplified drawing of daisy ? chained ncp3121?s vout1 vout2 vout3 c1 c2 c3 c3 c2 c1 c4 vout4 c4 when the first voltage rail has reached a specific voltage level, the next voltage rail is enabled and its rise is monitored until it has reached the power good trip point. at this point, the next voltage rail is enabled. this continues until all voltage rails have been enabled (see figure 46). power ? down sequencing is just the opposite of the power ? up sequence.
ncp3121 http://onsemi.com 23 figure 46. typical behavior of sequential mode en1 & seq2 seq1 & en2 ss1 ss2 vout1 0.8v 4v 4v (min) internal pg1 vout1 & vout2 (min) vout2 internal pg2 90% v fb (min) 10% v fb (min) pg1 pg2 0.8v 10% v fb 0.8v 0.8v 90% v fb
ncp3121 http://onsemi.com 24 figure 47. sequential mode ? power ? up figure 48. sequential mode ? power ? down figure 49. sequential mode ? power ? down figure 50. daisy chain of four outputs figure 51. olm of the 3rd output in daisy chain
ncp3121 http://onsemi.com 25 tracking voltage tracking is enabled by applying a ramp voltage to the track pin. when the voltage on the track pin is below 0.8 v, the feedback voltage will regulate to this tracking voltage. when the tracking voltage exceeds 0.8 v, tracking is disabled and the feedback voltage will regulate to the internal reference voltage. in this start ? up sequence, the tracking pin is used to match the output voltage ramps exactly. higher output voltage will continue to rise past the lower regulated point. this is achieved by dividing the higher output voltage by the same ratio as the lower voltage feedback components and connecting the divided voltage into the track pin of the lower voltage. track pins must be tied high in the normal operation (except in the tracking mode). the output voltage during tracking can be calculated with the following equation: v out v track 1 r5 r6 v track
0.8 v note: if enable control is not required, float the en/seq connections rather than pulling them to vin or a separate supply voltage. the ncp3121 will enable itself once vin crosses the input uvlo threshold. vout1 vout2 c master c master figure 52. tracking configuration enable disable r10 avin c13 c3 r8 vin out1 out2 gnd gnd gnd gnd gnd gnd gnd r9 r7 c4 d2 r3 r4 c8 gnd d1 gnd gnd c9 c10 gnd gnd r1 r2 c7 l1 l2 pg1 pg2 en1 seq1 en2 seq2 track1 track2 sw1 vin vin vin vin vin vin sw2 avin fb1 agnd comp1 ss1 gnd1 sw1 sw1 sw2 sw2 gnd2 ss2 comp2 agnd fb2 rt cmaster gnd r5 r6 r11 ncp3121
ncp3121 http://onsemi.com 26 figure 53. typical behavior of tracking configuration en1/seq1 & en2/seq2 ss1 vout1 & vout2 pg1 hyst+delay 0.8v 4v vout1 & ss2 90% v fb 1 (min) track2 pg2 0.8v (min) (min) 90% v fb 1 90% v fb 2 0.8v 0.8v hyst+delay
ncp3121 http://onsemi.com 27 figure 54. tracking mode ? power ? up figure 55. tracking mode ? power ? down figure 56. tracking mode of four outputs ? power ? up figure 57. tracking mode of four outputs ? power ? down when hiccup overload mode is detected on the slave channel only, the output voltage of the 2nd channel (slave) decreases. after the overload condition ends, the slave channel voltage remains low. if the slave channel should rise when the olm disappears, the configuration of the enable and soft ? start pins shown in figure 58 must be used. figure 58. augmented olm in tracking mode en2 pin 4k7 n ? channel transistor ss2 pin n ? channel transistor c ss2 = 4n7 v out1 for proper operation of the modified tracking mode, use an ss1 capacitor with a value at least 10 times higher than that of the ss2 capacitor.
ncp3121 http://onsemi.com 28 figure 59. master voltage ? start of olm figure 60. master voltage ? end of olm figure 61. master voltage ? start of augmented olm figure 62. master voltage ? end of augmented olm note: if the overload conditions are detected on the master channel only or on both channels together (master + slave), both output voltages increase when the overload conditions are released. mixed mode a (sequencing and tracking) the different modes can also be used together to achieve various combinations of power sequencing. mixed mode a demonstrates the configuration of tracking and sequencing for four outputs. the schematic and typical output behavior is shown in figure 63. mixed mode b shows the combination of tracking, sequencing and normal mode. note: as in the previous, and all subsequent examples, if enable control is not required, float the en/seq control connection rather than pulling it to vin or a separate supply voltage. the ncp3121 will enable itself once vin crosses the input uvlo threshold.
ncp3121 http://onsemi.com 29 figure 63. mixed mode, configuration a vout1 vout2 vout3 vout4 enable disable r10 c13 c3 r8 vin out1 out2 gnd gnd gnd gnd gnd gnd gnd r9 r7 c4 d2 r3 r4 c8 gnd d1 gnd gnd c9 c10 gnd gnd r1 r2 c7 l1 l2 pg1 pg2 en1 seq1 en2 seq2 track1 track2 sw1 vin vin vin vin vin vin sw2 avin fb1 agnd comp1 ss1 gnd1 sw1 sw1 sw2 sw2 gnd2 ss2 comp2 agnd fb2 rt c5 gnd r5 r6 r11 ncp3121 r21 c16 c1 r17 out1 out2 gnd gnd gnd gnd gnd gnd gnd r18 r16 c2 d3 r14 r15 c12 gnd d4 gnd gnd c14 c15 gnd gnd r12 r13 c11 l3 l4 pg1 pg2 en1 seq1 en2 seq2 track1 track2 sw1 vin vin vin vin vin vin sw2 avin fb1 agnd comp1 ss1 gnd1 sw1 sw1 sw2 sw2 gnd2 ss2 comp2 agnd fb2 rt c6 gnd r19 r20 r22 ncp3121
ncp3121 http://onsemi.com 30 figure 64. mixed mode of four outputs ? power ? up figure 65. mixed mode of four outputs ? power ? down
ncp3121 http://onsemi.com 31 mixed mode b (normal & sequencing & tracking) figure 66. mixed mode, configuration b enable disable seq en ncp3121 track out out1 seq en ncp3121 track out out2 seq en track out out3 seq en track out out4 seq en ncp3121 track out out5 seq en ncp3121 track out out6 tied high vout2 vout3 vout4 vout5 vout6 vout1 ncp3121 ncp3121 figure 67. mixed mode of six outputs ? power ? up figure 68. mixed mode of six outputs ? power ? down
ncp3121 http://onsemi.com 32 normal operation (no tracking, no sequencing) figure 69. normal operation configuration vout1 vout2 enable disable r_track avin c3 c13 r13 vin out1 out2 gnd gnd gnd gnd gnd gnd gnd c22 rt r23 c23 d21 r21 r22 c21 gnd d11 gnd gnd c1 c2 gnd gnd r11 r12 c11 l11 l21 pg1 pg2 en1 seq1 en2 seq2 track1 track2 sw1 vin vin vin vin vin vin sw2 avin fb1 agnd comp1 ss1 gnd1 sw1 sw1 sw2 sw2 gnd2 ss2 comp2 agnd fb2 rt c12 en1 enable disable en2 pg1 pg2 r14 r24 ncp3121
ncp3121 http://onsemi.com 33 figure 70. typical application behavior en1/seq1 en2/seq2 ss1 ss2 vout1 vout2 pg1 pg2 hyst + delay 0.8v 0.8v 0.8v 0.8v 4v 4v 90%vfb (min) 90%vfb (min) hyst + delay
ncp3121 http://onsemi.com 34 parallel operation parallel operation of ncp3121 circuit(s) has several advantages. one of the most important aspects is the capability to deliver a double output current. the major advantage is a reduced output voltage ripple in case of out ? of ? phase synchronization. the standard configuration is shown in figure 71. olm in parallel operation when olm is detected (e.g., a jump from 4 a on the output to 6 a), the output voltage decreases. when olm wears off, the output current must be decreased below 3.5 a. then, the output voltage is released and current can be increased again ? up to 4 a. figure 71. parallel operation configuration. enable disable r_track avin c3 c13 r13 vin out gnd gnd gnd gnd gnd c22 rt r23 c23 d21 gnd d11 gnd gnd c1 c2 gnd gnd r11 r12 c11 l11 l21 pg1 pg2 en1 seq1 en2 seq2 track1 track2 sw1 vin vin vin vin vin vin sw2 avin fb1 agnd comp1 ss1 gnd1 sw1 sw1 sw2 sw2 gnd2 ss2 comp2 agnd fb2 rt c12 en ncp3121
ncp3121 http://onsemi.com 35 figure 72. parallel operation of both outputs
ncp3121 http://onsemi.com 36 loop compensation a comp pin of the transconductance error amplifier is used to compensate the regulation control system. standard comp pin values are shown in the bom at the end of the datasheet. (see the compcalc program to determine customer preferred values.) to design the compensation components for conditions not described in table 6 and/or for tuning the compensation for specific requirements, the compcalc design tool is available from on semiconductor at no charge. visit http://www.onsemi.com/pub/collateral/compcalc.zip to download the self ? extracting program for ncp3121 loop compensation design assistance. there is an excel design tool for component selection. this design tool is available at http://www.onsemi.com/pub/collateral/ncp312x%20 dws.xls . table 6. compensation values example for typical output voltages vin [v] vout [v] freq [khz] iout [a] l11 [ h] c11 ? ceramic [ f] c13 [nf] r13 [k ] c14 [pf] r14 [ ] c15 [nf] 12 3.3 200 3 15 22 22 4.7 220 100 none 12 5 200 3 22 22 18 4.7 270 100 none 5 1.8 200 3 10 22 27 2.7 270 100 none thermal considerations the ncp3121 has thermal shutdown protection to safeguard the device from overheating when the die temperature exceeds 160 c. for the best thermal performance, wide copper traces and a generous amount of pcb printed circuit board copper should be used in the board layout. one exception to this is at the sw switching node, which should not have a large area in order to minimize the emi radiation and other parasitic effects. large areas of copper provide the best transfer of heat from the ic into the ambient air. pcb layout guidelines as in any switching regulator, the layout of the printed circuit board is very important. rapidly switching currents associated with wiring inductance, stray capacitance and parasitic inductance of the printed circuit board traces can generate voltage transients that can generate electromagnetic interferences (emi) and affect the desired operation. to minimize inductance and ground loops, the lengths of the leads indicated by heavy lines should be kept as short as possible. for best results, single ? point grounding or ground plane construction should be used. on the other hand, the pcb area connected to the sw pin (drain of the internal switch) of the circuit should be kept to a minimum in order to minimize coupling to sensitive circuitry. another sensitive part of the circuit is the feedback. it is important to keep the sensitive feedback wiring short. to ensure this, physically locate the programming resistors near the regulator. there should be a ground area on the top layer directly under the ic with an exposed area for connecting the ic exposed pad. any internal ground planes should be connected by vias to this ground area. additional vias must be used at the ground side of the input and output capacitors. the gnd pin also should be tied to the pcb ground in the area under the ic. when laying out the buck regulator on a printed circuit board, the following checklist should be used to ensure proper operation of the circuit: 1. rapid changes in voltage across parasitic capacitors and abrupt changes in current in parasitic inductors are major concerns for a good layout. 2. keep high currents out of sensitive ground connections. 3. avoid ground loops, as they pick up noise. use star or single ? point grounding. 4. for high power buck regulators on double ? sided pcbs, a single ground plane (usually the bottom) is recommended. 5. even though double ? sided pcbs are usually sufficient for a good layout, four layer pcbs represent the optimum approach to reducing susceptibility to noise. use the two internal layers as the power and gnd planes, the top layer for power connections and component vias, and the bottom layer for noise sensitive traces. 6. keep the inductor switching node small by placing the output inductor as close as possible to the chip. 7. use fewer, but larger, output capacitors; keep the capacitors clustered; and use multiple layer traces with heavy copper to keep the parasitic resistance low. 8. place the output capacitors as close to the output coil as possible. 9. place the comp capacitor as close as possible to the comp pin. 10. place the v in bypass capacitors as close as possible to the ic. 11. place the rt resistor as close as possible to the rt pin. 12. the exposed pad must be connected to a ground plane with a large copper surface area to dissipate heat.
ncp3121 http://onsemi.com 37 layout diagram figure 73. typical layout diagram
ncp3121 http://onsemi.com 38 typical application circuit figure 74. typical circuit diagram enable disable r1 c3 c13 r13 vin out1 out2 gnd gnd gnd gnd gnd gnd 100n r23 c23 d21 r21 r22 c21 gnd d11 gnd gnd c1 c2 gnd gnd r11 r12 c11 l11 l21 pg1 pg2 en1 seq1 en2 seq2 track1 track2 sw1 vin vin vin vin vin vin sw2 avin fb1 agnd comp1 ss1 gnd1 sw1 sw1 sw2 sw2 gnd2 ss2 comp2 agnd fb2 rt c12 en1 enable disable en2 pg1 pg2 r16 r26 c15 2a @ 5v 2a @ 3.3 v r14 c14 r24 c24 c25 c22 75k 5.1k 3.3k 100n 22n 4.7k nu rvin 100 100n 15u mbrs340 mbrs340 15u 22u 100n 100 220p 47k 15k 22u 22u 68k 13k 100 220p 4.7k 22n nu ncp3121
ncp3121 http://onsemi.com 39 figure 75. pcb layout example ? evaluation board v 2.11
ncp3121 http://onsemi.com 40 components: table 7. bill of materials for the typical application circuit bom of the ncp3121 ? evaluation board v2.11 qty value scale ref. designator vendor part number chip 1 qfn32, 5x5 mm ncp3121 on semiconductor resistors 3 100 1206 rv in , r14, r24 vishay rca1206100r0fkea 1 75 k 1206 r1 vishay rca120675kfkea 1 68 k 1206 r11 vishay rca120668k0fkea 1 13 k 1206 r12 vishay rca120613k0fkea 2 4.7 k 1206 r13, r23 vishay rca12064k70fkea 1 47 k 1206 r21 vishay rca120647k0fkea 1 15 k 1206 r22 vishay rca120615k0fkea 1 5.1 k 1206 r16 vishay rca12065k10fkea 1 3.3 k 1206 r26 vishay rca12063k30fkea capacitors 3 22 f 1210 c1, c11, c21 kemet c1210c226k4pac 4 100 nf 1206 c2, c3, c12, c22 epcos b37872a5104k060 2 22 nf 1206 c13, c23 epcos b37872a5223k060 2 220 pf 1206 c14, c24 epcos b37871k5221j060 inductors 2 15 h l11, l21 coilcraft do3340p ? 153 diodes 2 mbrs340t3 d11, d21 on semiconductor ordering information device package shipping ? NCP3121MNTXG qfn32 (pb ? free) 4000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
ncp3121 http://onsemi.com 41 package dimensions qfn32 5*5*1 0.5 p case 488am ? 01 issue o seating 32 x k 0.15 c (a3) a a1 d2 b 1 9 16 17 32 2 x 2 x e2 32 x 8 24 32 x l 32 x bottom view exposed pad top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e a 0.10 b c 0.05 c notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm terminal 4. coplanarity applies to the exposed pad as well as the terminals. plane dim min nom max millimeters a 0.800 0.900 1.000 a1 0.000 0.025 0.050 a3 0.200 ref b 0.180 0.250 0.300 d 5.00 bsc d2 2.950 3.100 3.250 e 5.00 bsc e2 e 0.500 bsc k 0.200 ??? ??? l 0.300 0.400 0.500 2.950 3.100 3.250 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 pitch 3.20 0.28 3.20 32 x 28 x 0.63 32 x 5.30 5.30 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncp3121/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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